1. Field of the Invention
This invention relates to an addressing system which is suitable for use in a computer system in which a plurality of processing units are capable of sharing a plurality of memories via independent address buses.
2. Description of the Prior Art
With considerable progress in large scale integrated circuit technology in recent years, high performance processing units are now available at relatively low costs. Thus, it is possible to carry into practice a system that employs a plurality of processing units in one piece of equipment to provide for enhanced performance in its entirety. In such a system, the effective utilization of memories and the universality of the system are desired; to meet the requirements, there has heretofore been proposed a computer system such, for example, as shown in FIG. 1.
In FIG. 1, a computer system, which is provided with a plurality of microprocessing units CPU1 to CPU3, is arranged so that memories MEM1 to MEM4 can be connected to a desired one of address buses BUS1 to BUS3 of the microprocessing units CPU1 to CPU3 through multiplexers MUX1 to MUX4, respectively. By switching the multiplexers MUX1 to MUX4, each microprocessing unit is permitted to use a desired one of the memories MEM1 to MEM4. Assuming that each of the memories MEM1 to MEM4 has, for example, 16K words capacity, the overall memory address space is such as shown in FIG. 2 which has a memory capacity of 64K words. In this case, setting the multiplexers, for example, MUX1 and MUX2 to connect the microprocessing unit CPU1 and the multiplexers MUX3 and MUX4 on the microprocessing units CPU2 and CPU3 respectively, the microprocessing unit CPU1 is able to use an address area 0000(H) to 7FFF(H), where H is the hexadecimal digit, of addresses assigned to the memories MEM1 to MEM4, whereas the microprocessing units CPU2 and CPU3 are able to use an address area 8000(H) to BFFF(H) and an address area C000(H) to FFFF(H), respectively. Since the setting of the multiplexers MUX1 to MUX4 can be freely altered in accordance with the memory capacity necessary for the microprocessing units CPU1 to CPU3, the universality of the system can be enhanced.
Incidentally, as will be appreciated from the memory map of FIG. 2, in the case of using the memories MEM1 to MEM4 separately by the microprocessing units CPU1 to CPU3, the leading addresses of the memories that are accessed by the microprocessing units except one (CPU1 in the illustrated example) do not naturally start with 0000(H), and the leading addresses also vary with modification of the memory allocation. Therefore, an address that is desired to be fixed for each microprocessing unit, such as, for example, a start address immediately after power source connection or a leading address of a stack for a subroutine, does not remain constant. Furthermore, it is impossible to adopt a direct addressing method which is effective for use in producing short word length instructions to reduce the execution time and the number of program steps used, for example, in an addressing method which is effective for an address in a limited range such as the data stored in the address area from the address 0000(H) to the address 00FF(H). Accordingly, each time the memory allocation to the microprocessing units CPU1 to CPU3 is modified, hardware and software must also be modified. This makes the modification of the memory allocation essentially difficult, and since the above-mentioned addressing method cannot be employed, the number of program steps inevitably increases.